A portion of the disclosure of this patent document contains material which is subject to copyright protection or to mask-work protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
A mask work is a kind of map or blueprint used to design and manufacture a semiconductor chip or circuits that are fabricated on like materials. The mask work defines the design of the chip in three dimensions, since a semiconductor chip consists of several layers of electronic circuits and elements that are laid down one atop another. The mask work images may be in pictorial or photographic form or broken down into digital numerical form for storage in a computer. Furthermore, the mask-work owner reserves all rights to the integrated circuit topography of mask-work examples presented hereinafter.
The present invention generally relates to an electrically conductive attachment. More specifically, the present invention relates to use of a thickened electrical conductor material for connection between two conductive segments located on facing surfaces.
Numerous components are currently fabricated which methodologically require coordination between a conductive region (or segment) on a first surface and another conductive region (or segment) on a facing surface. This type of construction is typical in the fabrication of liquid crystal display (hereinafter xe2x80x9cLCDxe2x80x9d) panels. The LCD panels consist of two plates with an encapsulated liquid crystal film layer there between. The encapsulation is to prevent the incursion of moisture, air, or environmental contaminants. Furthermore, the plates (generally of glass, silicon, or plastic) include at least one rigid plate and at least one transparent (or substantially non-opaque) plate. Most well-know applications use two rigid plates. In order for a region of the liquid crystal material to obtain a predetermined optical property, an electric field is established above a threshold value and thereafter quickly discontinued. In order for this predetermined optical property to be cancelled, an electric field is establishedxe2x80x94generally above a lower threshold value and then gradually discontinued.
In order to apply either electric field to a selected region of the LCD (especially cholesteric liquid crystal), there are pre-positioned conductors on opposite interior faces of the plates. Furthermore, in order to electrically access these conductors, there is a conductive path from an exterior contact point to each respective conductor. By this means, selecting from pairs of exterior contacts will allow a controller to address the optical property of a selected pixel regionxe2x80x94in the case where conductors on one face are parallel x-axis lines and conductors on the opposite face are parallel y-axis lines. Alternatively, there are icon oriented displays (rather than general purpose pixel type displays) where specific conductive patterns are established on regions of opposite faces and conductive lines are arranged respectively thereto from the plate edges in order to facilitate addressing of the icons; or more specifically their respective optical property setting.
Generally, the conductors are selected in LCDs to be transparent conductors (such as indium-tin-oxide) but very narrow visible conductive lines also are used in particular applications. These conductors are applied to the surface of the plate(s) during a fabrication process by using deposition and etching techniques for high-resolution arrangements, and with silk-screening type techniques for lower resolution applications.
There is a longstanding, well accepted axiom in the procedure for designing and fabricating LCD plate pair units, and the likes, that one needs conductive contact points on at least one exterior edge of each plate in order to address opposing pairings of conductors on opposite faces. This long accepted need results in plate pairs having at least two edge regions that do not participate in the display area per se, but only exist to provide the functionality of connective access to specific regions of the interior faces. Because there are two edge regions, there is a need in the packaging of these plate pair products for two sets of attachments; one for each edge region. Simply stated, there is a need in the art for a reduction in the number of such attachments; particularly since each independently contributes to the fabrication cost per unit. Nevertheless, it would be a significant advance in the art for the at least two edge regions to be unifies into a lesser number of contiguous regions; and presumably optimally into one contiguous region.
One might expect that electrical interconnections between facing surfaces to be a standard method for overcoming this apparent topological over engineering, but no such fabrications technique has been forthcoming.
One might consider p-type or n-type materials that are selectively deposited (using optical-mask transfer techniques) on semiconductor substrates functionally as examples of inter-layer electrical connectivity. However, layering of these types of materials is explicitly for implementing active electrical elements, such as memory, gates, logic circuits, counters, etc.; or on a more refined level of analysis, for partial capacitance, partial resistance, etc. and not for simple electrical connectivity across facing surfaces. Actually, the deposition and etching techniques implements in mask work products incorporating p-type or n-type materials are specifically characterized by building up circuit functionally onto a single surface; and not building up two circuit halves for eventual aligned interface and electrically circuit interconnectivity. Fabricating three-dimensional circuits in this way would suffer from certain lower precision available in mechanical alignment between the plate surface faces than in the deposition and etching. Hence, one would never consider a hybrid process of building up semiconductor layers simultaneously with even a single mechanically aligned pairing between two of those layers.
Alternatively, one might consider solder points on printed circuit boards (hereinafter xe2x80x9cPCBxe2x80x9d) as perhaps contributing to some reduced topological complexity for multiple PCB layers. However these configurations are integrated by design with a plurality of pre-drilled component attachment holes; and are not present for actually implementing simple electrical contact between otherwise facing PCB layer surfacesxe2x80x94nor can one easily find a reason for what such a sandwich construction would be trying to accomplish.
Collectively, it appears that in the world of layered electrical components having interstitial dielectric thin film interfacing (such as LCDs) there has been no novel implementations of simple electrical topological simplifications using inter layer electrical connections. While U.S. Pat. No. 5,283,948 U.S. Pat. No. 6,063,647 and U.S. Pat. No. 6,239,384 each describe a form of perpendicular connector that might be useful for implementing basic topological simplifications in such systems, no evidence of such application has been forthcoming. Thus, it is surprising that in the super competitive high tech CAD/CAM type electronic component fabrication environment of LCDs there has been no progressive solution for reducing the electrical connective architecture; which is one of the most expensive per unit aspects of these components; after the overall fabrication setup costs have been amortized.
The present invention relates to a fat conductor. The fat conductor of the present invention is especially useful for electrically interconnecting between a pair of substantially parallel plates, wherein each of the plates has a prearranged pattern of conducting surface coating regions on the interior face side thereof. The fat conductor is specifically for use in sandwiched constructions of the plates having encapsulated dielectric film there-between. In fact, the major accomplishment of the fat conductors of the present invention resides in the facility to places these fat conductors substantially anywhere on the plate; and not just in the unseen exterior peripheral frame region of the plate.
Embodiments of the fat conductor of the present invention include three interrelated elements: conductive surface coating pads (matching), a perimeter wall (around one of the pads), and a conductive paste (for electrically connecting between the pads within the region restricted within the perimeter wall). Furthermore, for simplicity of understanding, the most useful aspect of the present invention lies in the ability to locate viable fat conductors substantially anywhere that a conductive pad can be fabricated, especially in central areas of substrate plates; and not restricted to placement in the unseen exterior peripheral frame region of the plate which are often hidden from view by plate holders. In contradistinction, the exterior peripheral frame region of the plate is generally characterized as not being circumscribed by a dielectric material layer on all sides, by reason of environmental encapsulation functions that are generally engineered in the region of the plate edges.
Note that sometimes in the literature xe2x80x9cconductive pastesxe2x80x9d are called xe2x80x9cconductive creamsxe2x80x9d especially in cases where they are applied using silk screening techniques rather than sputtering or deposition techniques. Elsewhere in the literature, these viscous conductive xe2x80x9cpastesxe2x80x9d are called xe2x80x9cthick non-volatile conductive inksxe2x80x9d. Generally, conductive pastes rely on a high quantity of fine suspended conductive particles (e.g. powered silver, gold, palladium, etc.) to achieve the basic conductive properties. However, sometimes the conductive properties are achieved using conductive carrier materials in the paste, such as conductive polymers or conductive metallo-organics, etc. Specific election of a practical cost effective conductive paste is generally in consideration of electro-chemical interactions with contiguous or proximate materials, available environmental encapsulations, galvanic isolation, etc., and in consideration of other environmental use factors (e.g. operating temperature, cross talk effects, etc.).
One should appreciate from the outset that, while there may be many useful applications of a solitary fat conductor between a pair of plates, it is a fundamental objective of the present invention to address improvements in the fabrication of liquid crystal displays; and related flat panel type constructions wherein a large number of fat conductors are used in a single construction. For example, in the case of LCDs, the construction would substantially require about the number of rows or the numbers of columns (which ever is the lesser number) in at least one layer of the display. Fabrications of components having only a single instantiation of a fat conductor therein are beyond the scope of the present invention. The present invention is directed to components having a plurality of fat conductors therein, and typically to those having a large number of fat conductors therein. Furthermore, one should be aware that the dielectric film located between the plates will generally require at least some global encapsulation against the intrusion of moisture, air, and other environmental contaminants. The mechanics of such encapsulation, for a region between plates or for a pair of plates or for xe2x80x9csandwichesxe2x80x9d including more than two plates, is beyond the scope of the present application; and is generally well understood by those whose art includes the filling and sealing of dielectric film between platesxe2x80x94such as in the case of LCDs.
Generally, that is to say for convenience of understanding, one can portray the fat conductor of the present invention as being an electrically conductive paste that is laterally constrained within a perimeter wall and operable along a normal axis between the two pads. Simply stated, the conductive paste when properly situated between the pads is a xe2x80x9cfat conductor,xe2x80x9d and when properly constrained within the perimeter wall, continues to perform as a conductor; since otherwise the conductive paste will either disperse until the critical amount required to maintain electrical contact is depleted, or until sufficient peripheral impurities permeate the conductor and thereby xe2x80x9cspoilxe2x80x9d the desired electrical conductive propertyxe2x80x94for example by introducing amorphous capacitance regions, etc.
According to the above-mentioned embodiments of the fat conductor of the present invention, the pads are two thin conductive surface coating pads that are of substantially complementary size. One of the two pads is located on each facing plate. The pads are situated to face each other when the plates are sandwiched together. Each pad has an associated conductive surface coating path on its respective surface. For many applications, it has been found that pad shapes with large perimeter to area rations are preferred. The simplest of such pad designs is a pad with a concentric central void. For example a circular pad with a circular central void area or a rectangular pad with a rectangular void area. In principal, for larger pads it is expected that the central area be a tessellation (regular, irregular or recursive) of interconnected mini-pads. It appears that the functionality of the electrical connection between the pad and the paste is generally improved according to these design criteria. Nevertheless, there are pastes that do not nee this extra level of pad design; and there are certainly pad designs that will accommodate pastes of otherwise poor interface qualities.
According to the above-mentioned embodiments of the fat conductor of the present invention, the perimeter wall is of adhesive that is arranged around one of the pads. This arrangement serves two purposes. Firstly, it contributes to the isolation of the conductive paste from the dielectric film. Secondly, it contributes to overall adhesion between the plates. Nevertheless, since adhesion between the plates can be achieved externally through correct choices in the packaging of the plates, the key property is related to marinating adequate separation between the paste and the film. Certainly, the operating conditions intended for the final apparatus of plates, fat conductors, etc., will substantially contribute to the precise specification of the adhesive; since temperature, vibration, radiation, and other exogenous factors affect the permeability of the adhesive and the miscibility of the film into the pastexe2x80x94and substantially not less importantly, of the paste into the film, and of the adhesive into either.
According to the above-mentioned embodiments of the fat conductor of the present invention, a conductive paste is situated within the perimeter wall such that when the plates are sandwiched together there is formed an electrically conductive connection between the pads via the paste. According to the simple embodiments of the present invention, the paste functions as a simple passive electrically conductive shunt between the pads, thereby closing a path in a circuitxe2x80x94having both pads as topological member thereof. According to more sophisticated embodiments of the present invention, the paste includes at least one active element therein; thereby effecting the functionality of a circuitxe2x80x94having both pads as topological member thereof.